1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly to a buried bit line-type semiconductor memory device which is improved in order to increase the processing accuracy of a storage node.
2. Description of the Background Art
Lately, a demand for semiconductor memory devices has been increased rapidly thanks to the spread of information devices such as a computer. Functionally, the semiconductor memory device having a large storage capacity and operating at a high operational speed is required. Accordingly, development of the technology for high integration, quick response and high reliability of the semiconductor memory device has been carried out.
Among semiconductor memory devices, a DRAM (Dynamic Random Access Memory) which allows random input/output of memory information is known. Generally, a DRAM includes a memory cell array which is a memory region storing a large amount of memory information and a peripheral circuitry which is required for external input-output.
FIG. 1 is a block diagram showing a structure of a general DRAM. Referring to FIG. 1, a DRAM 50 includes a memory cell array 51 storing data signals of the memory information, a row and column address buffer 52 for receiving an external address signal (a signal for selecting a memory cell constituting an unit memory circuit), a row decoder 53 and a column recorder 54 for designating the memory cell by decoding the address signal, a sense refresh amplifier 55 for amplifying and reading the signal stored in the designated memory cell, a data-in buffer 56 and a data-out buffer 57 for data input/output, and a clock generator 58 generating a clock signal.
Memory cell array 51 occupies a large area on a semiconductor chip. A plurality of memory cells each storing unit memory information are provided in a matrix in memory cell array 51.
FIG. 2 is an equivalent circuit for 4 bits of memory cells constituting the memory cell array. The memory cell shown is a so-called 1 transistor-to-1 capacitor type memory cell which is structured with one field effect transistor and one capacitor connected thereto. This type of memory cell has a simple structure so that higher degree of integration of the memory cell array can easily be improved, and thus it is often used in a DRAM which requires a large capacity.
Referring to FIG. 3, such transistor and capacitor are formed within a field region 2a in the surface of a semiconductor substrate 1. One field region 2a is isolated from another field region 2a by an isolation oxide film 2.
In table 1 below, characteristics of various semiconductor devices described in this specification are listed. First, second, and third conventional examples will be described below, followed by the description of the present invention.
TABLE 1 ______________________________________ Plane Layout of the Vertical Structure field region ______________________________________ 1st unburied bit line- half pitch conventional type stacked cell arrangement example structure structure 2nd buried bit line-type half pitch conventional stacked cell arrangement example structure structure half pitch 3rd buried bit line-type arrangement conventional stacked cell structure (an example structure obliquely arranged field region) Present buried bit line-type quarter pitch Invention stacked cell arrangement structure structure ______________________________________
First Conventional Example
FIG. 4 is a plan view of a semiconductor device according to a first conventional example, and FIG. 5 is a sectional view of FIG. 4 taken along line A-B.
Referring to these drawings, the semiconductor device includes a word line 4 and a bit line 15 which cross each other. A transfer gate transistor and a stacked type capacitor are provided in the vicinity of the crossing of word line 4 and bit line 15. The transfer gate transistor includes a pair of source/drain regions 6, 6 which are formed in the surface of silicon substrate 1, and a gate electrode (a word line) 4 which is formed on the surface of silicon substrate 1 with an insulating layer posed therebetween.
The stacked type capacitor contacts one of the source/drain regions 6, and includes a storage node (a lower electrode) 11 which is extending to the upper portion of gate electrode 4. A contact portion of storage node 11 and source/drain region 6 is called a storage node contact 50. A capacitor insulating film 12 covers the surface of storage node 11. A cell plate 13 is provided over storage node 11 with capacitor insulating film posed therebetween.
An interlayer insulating film 20 is provided on silicon substrate 1 to cover the transfer gate transistor and the stacked capacitor. A bit line contact hole 52 is provided in interlayer insulating film 20 for exposing a bit line contact 51. Bit line 15 is connected to one of the source/drain regions 6 through bit line contact hole 52. Source/drain regions 6, bit line contact 51, and storage node contact 50 are formed within field region 2a.
One field region 2a is isolated from another field region 2a by field oxide film 2.
FIG. 6A is a plan view of the semiconductor device showing the entire field region 2a which is taken out from FIG. 4 for easier understanding. FIG. 6B is a sectional view taken along line B--B in FIG. 6A.
Referring to FIGS. 4, 6A, and 6B, a plurality of field regions 2a are disposed at a predetermined pitch in the direction where bit line 15 runs. Next to a row of field region 2a indicated by a reference character a, a field region 2a indicated by reference character b is provided in parallel. Also, next to a row of field region indicated by a reference character b, a field region 2a indicated by a reference character c is provided. Field region 2a indicated by the reference character a and field region 2a indicated by the reference character b are formed shifted from each other by 1/2 pitch in the running direction of a bit line.
As for the relationship between a row of the field region indicated by the reference character b and the field region indicated by the reference character c, field region 2a indicated by the reference character b and field region 2a indicated by the reference character c are also formed shifted from each other by 1/2 pitch.
FIG. 7 shows an arrangement of field regions 2a in the vicinity of the contact portion of bit line 15 and sense amplifier 54 of a close packed folded bit-line cell array.
In the semiconductor memory device having a half pitch arrangement structure as well as unburied bit line-type stacked cell structure such as shown in FIG. 4 (the first conventional example), it is necessary to increase a dimension SNx (a length of the storage node) and a dimension SNy (a width of the storage node) in order to increase the capacitance of the capacitor. However, predetermined dimensions of SNmin (a distance between two adjacent storage nodes) and SNcp (a distance from an end of the storage node to an end of the cell plate) should be reserved, so that there is a limitation for increasing SNx. Thus in the semiconductor memory device according to the first conventional example, it was difficult to reserve a sufficient capacitance of the capacitor because SNx could not be increased.
Although a close packed folded bit-line cell array of quarter pitched arrangement immune to noise is disclosed (The Institute of Electronics, Information and Communication Engineers of Japan, National Spring Meeting, 1991, C-665), a field region with a quarter pitched arrangement, and a buried bit line type stacked cell are not disclosed.
Second Conventional Example
In order to solve the problem of the first conventional example, a semiconductor memory device having a buried bit line-type stacked cell structure and a half pitch arrangement structure such as shown in FIG. 8 has been suggested as a second conventional example.
FIG. 9 is a sectional view taken along line A-B in FIG. 8, and FIG. 10 is a sectional view taken along line C-D in FIG. 8. In these figures, like reference numerals are given to the portions which are identical or corresponding to the members indicated in FIGS. 4 and 5.
Referring to these figures, the feature of the semiconductor memory device according to the second conventional example is that a cell plate 13 is formed above bit line 15, and thus bit line 15 is buried under cell plate 13. In the structure like this, there is no limitation for the dimension SNcp, so that the dimensions SNx and SNy can be increased. However, if the dimensions SNx and SNy are increased to the limit of processing accuracy of the storage node, the accuracy of processing storage node 11 will be deteriorated, because an end of storage node 11 is positioned close to bit line contact portion 51.
In order to solve the problem, a semiconductor device according to a third conventional example has been suggested. Prior to the description of the semiconductor device according to the third conventional example, a manufacturing process of the unburied bit line-type semiconductor device shown in FIG. 4 and a manufacturing process of the buried bit line-type semiconductor device shown in FIG. 8 will be compared with each other in the description below.
FIG. 11A schematically shows a manufacturing process of the unburied bit line-type stacked cell. The unburied bit line-type semiconductor device is manufactured through the steps of forming a field oxide film (155), forming a transfer gate (156), forming a storage node (157), forming a cell plate (158), and forming a bit line (159) in turn. Meanwhile, the buried bit line-type device is manufactured through the steps of forming a field oxide film (155), forming a transfer gate (156), forming a bit line (159), forming a storage node (157), and forming a cell plate (158) in turn, as shown in FIG. 11B.
Third Conventional Example
FIG. 12 is a plan view of a semiconductor memory device according to the third conventional example, and FIG. 13 is a sectional view taken along line A-B in FIG. 12. In FIG. 12, storage node 11 is supposed not to appear in the sectional view cut along line A-B: however, storage node 11 is shown in FIG. 13 for convenience, in order to clarify the characteristic part, although it is against the drawing rule.
The third conventional example has the buried bit line-type stacked cell structure and the half pitch arrangement structure as in the second conventional example. FIG. 14 shows the field region.
The third conventional example has such characteristics that a row of field region (a) and an adjacent row of field region (b) are formed shifted from each other by 1/2 pitch in the running direction of bit line 15 and that field region 2a is arranged obliquely to the running direction of bit line 15. In FIG. 14, the regions shown by dotted lines, which are for clarifying the shift of pitch, are phantom arrangements of the field regions assuming that field region 2a is not arranged obliquely.
In the third conventional example, source/drain regions 2a , the storage node contact, and the bit line contact are formed in the obliquely arranged field region, further detailed description of which will be given referring to FIGS. 12 and 13.
Referring to FIGS. 12, 13 and 14, field region 2a is arranged obliquely to the running direction of the bit line 15. Gate electrode 4 is formed on silicon substrate 1. Interlayer insulating film 20 is formed to cover gate electrode 4. Bit line contact hole 51h is formed in interlayer insulating film 20 in order to expose bit line contact 51. Bit line 15 is connected to one of the source/drain regions 6 through bit line contact hole 51h. Interlayer insulating film 18 is formed on silicon substrate 1 to cover bit line 15. Storage node 11, which is the lower electrode of the capacitor, is formed on interlayer insulating film 18. Storage node 11 is connected to the other one of the source/drain regions 6 by storage node contact 50 through storage node contact hole 50h which is formed in interlayer insulating films 18 and 20.
The problems of the semiconductor memory device according to the third conventional example will be described.
FIG. 15 is an enlarged perspective view of an end 11a of storage node 11 in FIG. 13. Referring to FIGS. 12, 13 and 15, the dimensions SNx and SNy should be increased to the limit of the processing accuracy in order to increase the plane area of storage node 11. When the dimensions SNx and SNy are increased, end 11a of storage node 11 is supposed to be located above bit line contact hole 51h.
FIG. 16 is a sectional view of the semiconductor device during patterning of storage node 11. A residue 11b of storage node 11 easily adheres to an inclined portion 18a in the recess in interlayer insulating film 18, because end 11a of the storage node is placed above bit line contact hole 51h. Storage node 11 and adjacent storage node 11 are connected by this residue 11b, and accordingly storage nodes 11 and 11 will be short-circuited.
The problem of a residue existing at inclined portion 18a is also found in FIG. 17 where storage nodes 11 are formed in a manner shifted to each other. More specifically, referring to FIG. 18 taken along line D--D of FIG. 17, an end 11a of storage node 11 is formed on a concave inclined portion 18a on interlayer insulating film 18. Therefore, as long as the half pitch arrangement structure is employed, the problem of residue at inclined portion 18a cannot be avoided no matter how the storage nodes are shifted with respect to each other.
Meanwhile, in the buried bit line-type semiconductor memory device shown in FIG. 13, the following problem has also occurred, i.e., in the buried bit line-type memory cell referring to FIG. 13, the interline capacitance between word line 4 and bit line 15 was increased because the word line 4 and bit line 15 come close to each other.